DevConf.US 2022

The flexibility, high performance and power efficiency of Field Programmable Gate Arrays (FPGAs) has resulted in greater ubiquity in both cloud and edge environments. However, the existing state-of-the-art vendor tooling for FPGA bitstream generation lacks a number of features that are critical for high productivity, which in turn results in long turnaround times (hours to days) and substantially limits the manner in which FPGAs can be used. Since this tooling is also closed source, it cannot be modified to incorporate additional functionality. On the other hand, while there are a number of open source alternatives, these tools currently only deliver a fraction of the hardware quality as vendor tooling - thus making their use impractical for most workloads. Our work is aimed at bridging this gap between open-source and vendor tooling for FPGA bitstream generation, in order to make the former a viable solution to the low productivity in FPGA development. To do so, we first build a synthetic benchmark set which can be used to identify and analyze policy decisions made by tools that impact generated hardware quality. Next we apply these benchmarks to open source tools in order to determine bottlenecks or suboptimal policies. Finally, we optimize the identified policies - this can be done manually or through reinforcement learning (in order to automatically determine the best strategy for a given design). To demonstrate the effectiveness of our approach, we apply it to Packing - a critical step in the bitstream generation process which impacts device resource utilization. The open source tool we have used is Versatile Place and Route (VPR). In this talk, we will look at the details of packing policies, sythetic benchmarks that we built and the metrics we developed to determine packing quality.