DevConf.US 2022

FPGAs have long filled crucial niches in networking and edge by combining powerful computing/communication, hardware flexibility and energy efficiency. However, there are challenges in development and design portability in FPGAs: the entire hardware stack is commonly rebuilt for each deployment.
Operating System-like abstractions, referred to as Shells or hardware Operating Systems (hOS), can help reduce the development complexity of FPGA workloads by connecting the IP blocks needed to support core functionality e.g. memory, network and I/O controllers. However, existing hOS have a number of limitations, such as, use of IP blocks which cannot be modified, fixed resource overhead, tightly coupled IP blocks, and unique interfaces which reduces design portability. As a result, existing hOS are typically only useful for specific workloads, interfaces, vendors and hardware deployed in a specific infrastructure configuration (e.g SmartNIC).
In this work, we present the Dynamic Infrastructure Services Layer (DISL) for FPGAs as a solution to the above limitations. DISL is a framework that allows developers to generate hOS that can be either generic or customized based on user requirements such as the target workload, FPGA size, FPGA vendor, available peripherals etc. DISL does so through a number of features such as: i) use of open source, heavily parameterized, and vendor agnostic IP blocks, ii) a modular layout and configurable interconnect, iii) standard Application Programming Interfaces (APIs) at both the inter and intra device level, iv) automatic detection of an application’s hOS requirements for components and connectivity (both compile-time and run-time) during compilation, and v) a DISL software development kit (SDK) which is integrated into the Linux kernel and gives user access to tools for configuring, monitoring, debugginging and various other utilities that reduce the complexity of developing, deploying and interfacing FPGA workloads.